In recent years, communication systems are required to achieve extremely wide band and fast speed. Therefore, a sampling rate of used in a ΔΣADC is extremely fast, exceeding several hundred MHz. The ΔΣADC uses ΔΣ modulation for converting an analog signal into a one-bit digital signal, thus capable of suppressing quantization error near DC by noise shaping.
When a generally-available quantizer is used to perform quantization, a quantization noise is distributed over all frequencies. In contrast, when a ΔΣ modulator is used to perform quantization, a quantization noise is suppressed near DC, and a quantization noise is formed in high frequency. Such characteristic of the ΔΣ modulator is called noise shaping characteristic.
By the way, in recent years, systems requiring a plurality of high frequency sections are expected, such as MIMO (Multiple Input Multiple Output), MRC (Maximum Ratio Combining), and diversity. In such system, reduction in the size of the circuit is requested. More specifically, in order to reduce the circuit scale, MIMO, MRC, or diversity is requested to time-divisionally use high frequency sections to share the circuit.
Patent literature 1 and patent literature 2 disclose time-division ΔΣADCs. The time-division ΔΣADCs disclosed in patent literature 1 and patent literature 2 perform time-division process for each one of sample times to switch to another sequence. Therefore, the speed of target time-division relies on the sample time. More specifically, in a system in which two sequences of signals including the first sequence and the second sequence are time-divisionally combined, the time-division ΔΣADC alternately selects signals from different sequence, e.g., first choosing a sample from the first sequence, then choosing a sample from the second sequence, and then choosing a sample from the first sequence. Then, the time-division ΔΣADC handles the signal sequence in which these signals are arranged. In this case, it is necessary for the time-division ΔΣADC to time-divisionally combine the plurality of signal sequences using a switch.
When an external component is used as the switch, there is a limitation in the switching speed. On the other hand, the sampling rate of the ΔΣADC is extremely fast, exceeding several hundred MHz. Therefore, there is a limitation in the switching speed of the switch, and when the switching speed of the switch is about 100 MHz, it is necessary to reduce the actual sampling rate of the ΔΣADC to about 100 MHz when a conventional technique is simply used.